1. Field of the Invention
The present invention generally relates to a parallel compression test circuit of a memory device, and more specifically, to a technology of sequentially operating input/output amplifiers in a parallel compression test to disperse peak current and reduce noise.
2. Description of the Prior Art
FIG. 1 is a block diagram illustrating a conventional parallel compression test circuit of a memory device.
The conventional parallel compression test circuit of FIG. 1 comprises a memory unit 10, a compression comparing unit 20, a global input/output driving unit 30, an output driving unit 40, an input/output amplification control unit 50 and a global input/output driving control unit 60.
The memory unit 10 includes four banks 12, bit line sense amplifiers 14 and input/output sense amplifiers 16. Each of the input/output sense amplifiers 16 is activated by an input/output amplification control signal IOAEN outputted from the input/output amplification control unit 50.
The compression comparing unit 20 compares each data in input/output lines IOQ0˜IOQ3 which is outputted from each bank 12 in a compression test. Although the example for compressing and comparing data in 16 input/output lines is described herein, the number of input/output lines for compressing and comparing data can be adjusted if necessary.
The global input/output driving unit 30 includes a plurality of global input/output drivers. The global input/output drivers 34 corresponding to the number of banks drive data in one of the input/output lines IOQ0˜IOQ3 in response to a normal input/output driving control signal GIOENN outputted from the global input/output driving control unit 60 in a normal mode, and output the driven data to global input/output lines GIO0˜GIO15. In a compression test mode, the global input/output driving units 30 drive signals IOCMP0˜IOCMP3 outputted from the compression comparing unit 20 in response to a test global input/output driving control signal GIOENT outputted from the global input/output driving control unit 60, and output the driven data to the global input/output lines GIO0˜GIO3. The rest global input/output drivers 32 drive data in one of the input/output lines IOQ0˜IOQ3 in response to the normal global input/output driving control signal GIOENN only in the normal mode, and outputs the driven data to the global input/output lines GIO0˜GIO15.
The output driving unit 40 drives data in the global input/output lines GIO0˜GIO15 to output the driven data externally in the normal mode, and drives data in the global input/output lines GIO0˜GIO3 to output the driven data in the compression test mode.
FIG. 2 is a circuit diagram illustrating the input/output amplification control unit 50 of FIG. 1.
The input/output sense amplifier control unit 50 comprises a delay unit 52, inverters IV1˜IV3, and a NAND gate ND1.
The inverter IV1 inverts a signal YPR which represents a read operation period, and the delay unit 52 delays an output signal from the inverter IV1 for a predetermined time T1.
The inverter IV2 inverts an output signal from the delay unit 52, the NAND gate ND1 performs a NAND operation on output signals from the inverters IV1 and IV2, and the inverter IV3 inverts an output signal from the NAND gate ND1 to output an input/output amplification control signal IOAEN.
FIG. 3 is a circuit diagram illustrating the global input/output driving control unit 60 of FIG. 1.
The input/output driving control unit 60 comprises a delay unit 62, inverters IV4˜IV7, and NAND gates ND2 and ND3.
The inverters IV4 and IV5 sequentially invert the test mode signal TPA, and the delay unit 62 delays the input/output amplification control signal IOAEN for a predetermined time T2.
The NAND gate ND2 performs a NAND operation on the input/output amplification control signal IOAEN and an output signal from the inverter IV4, and the inverter IV6 inverts an output signal from the NAND gate ND2 to output the normal global input/output driving control signal GIOENN.
The NAND gate ND3 performs a NAND operation on output signals from the delay unit 62 and the inverter IV5, and the inverter IV7 inverts an output signal from the NAND gate ND3 to output a test global input/output driving control signal GIOENT.
FIG. 4 is a timing diagram illustrating the operation of the parallel compression test circuit of FIG. 1.
The input/output amplification control unit 50 outputs the input/output amplification control signal IOAEN having a pulse width corresponding to the delay time T1 of the delay unit 32 in response to the signal YPR which represents the read operation period.
The input/output amplifier 16 re-amplifies data amplified by the bit line sense amplifier 12 during a high active pulse period of the input/output amplification control signal IOAEN to output the output signals IOQ0˜IOQ3. Here, the output signals IOQ0˜IOQ3 from the input/output amplifier 16 are signals obtained by amplifying data in 16 input/output lines.
The output signals IOQ0˜IOQ3 from the input/output amplifier 16 are inputted the compression comparing unit 20 and the global input/output driving unit 30.
Each compression comparator 22 of the compression comparing unit 20 compresses and compares the output signals IOQ0˜IOQ3 of the input/output amplifier 16 to output comparison signals IOCMP0˜IOCMP3, respectively.
The global input/output driving unit 30 includes global input/output drivers 32 corresponding to the number of input/output lines in each bank 12. Each bank 12 comprises at least one or more of the parallel global input/output drivers 34 for selectively driving results of the normal or test modes.
In the normal mode, when the normal global input/output driving control signal GIOENN outputted from the global input/output driving control unit 60 is activated to a high level, all global input/output drivers 32 and 34 of the global input/output driving unit 30 are activated to drive and output the output signals IOQ0˜IOQ3 from the input/output amplifier 16 to the global input/output lines GIO0˜GIO15. All output drivers 42 of the output driving unit 40 drive and output data in the global input/output lines GIO0˜GIO15.
In the compression test mode, when the test global input/output driving control signal GIOENT outputted from the global input/output driving control unit 60 is activated, the parallel global input/output driver 34 of the global input/output driving unit 30 is activated to drive the comparison signals IOCMP0˜IOCMP3 outputted from the compression comparator 22 and output the driven signals to the global input/output lines GIO0˜GIO3. The output drivers 42 in the output driving unit 40 drive and output data in the global input/output lines GIO0˜GIO3.
In the normal operation, a selected bank is only operated, so that the input/output amplifier 16 and the global input/output driver 32 in the selected bank are However, in the compression test operation, the input/output amplifier 16 receives the input/output amplification control signal IOAEN outputted from the input/output amplification control unit 50, so that data of 64 bits are simultaneously outputted by 16 bits in each bank.
The compression comparing unit 20 simultaneously outputs the comparison signals IOCMP0˜IOCMP3 interchangeably in the banks, and the global input/output driving unit 30 receives the global input/output driving control signals GIOENN and GIOENT outputted from the global input/output driving control unit 60, so that data are simultaneously outputted interchangeably in the banks.
As a result, since all of the input/output amplifiers 16 are simultaneously operated, the peak current becomes larger and noise is generated.